The present invention generally relates to optical semiconductor devices and more particularly to a planer photodetection device suitable for mounting on a substrate according to a flip-chip process.
Semiconductor photodetection devices are key elements in the field of optical telecommunications as well as in the newly emerged field of multi-media. In multi-media applications, image data and audio data are processed together with other information such as text information. Thus, there is a need for processing huge amount of information in the multi-media applications, and such huge amount of information is transmitted through an optical fiber cable in the form of optical signals. In order to reduce the cost of multi-media systems and apparatuses, there is a demand for a planar semiconductor photodetection device that allows mounting upon a printed circuit board or a tape lead by a flip-chip process.
The inventor of the present invention has previously proposed a planar photodetection device suitable for flip-chip mounting. See, for example, U.S. Pat. No. 5,107,318, or Makiuchi, et al., IEEE Photonics Technology Letters, vol.3, no.6, June 1991.
FIG. 1 shows the construction of such a conventional semiconductor photodetection device 10 proposed by the inventor.
Referring to FIG. 1 showing a semiconductor photodetection device 10, the device 10 is mounted upon a ceramic support substrate 1 carrying thereon wiring patterns 1a and 1b and includes a layered semiconductor body that in turn includes an InP substrate 2 of the n-type, wherein the substrate 2 carries thereon an InP layer 3 of the n.sup.+ -type. Further, an undoped InGaAs layer 4 is grown on the InP layer 3 and an InP layer 5 of the n.sup.- -type is grown on the InGaAs layer 4, wherein the n.sup.- -type InP layer 5 includes p-type regions 5a and 5b doped by a diffusion of Zn.
It should be noted that the p-type regions 5a and 5b has a surface on which conductor layers of Au, Zn and Au are deposited consecutively (Au/Zn/Au), wherein the conductor patterns thus deposited are heat-treated to form an ohmic electrode in each of the p-type regions 5a and 5b. Further, those parts of the regions 5a and 5b that are not covered by the ohmic electrodes are covered by SiN patterns 6a and 6b. Thus, the SiN pattern 6a covers the exposed surface of the p-type region 5a while the SiN pattern 6b covers the exposed surface of the p-type region 5b. In addition, a polyimide layer 7 is provided on the InP layer 5 such that the polyimide layer 7 buries the SiN patterns 6a and 6b underneath, and the polyimide layer 7 is formed with a contact hole that exposes the ohmic electrode in each of the p-type regions 5a and 5b. Further, metal bumps 8a and 8b are provided in contact with the ohmic electrodes thus formed on the p-type regions 5a and 5b, via respective contact holes.
As shown in FIG. 1, the layered semiconductor body thus formed is turned over and mounted upon the support substrate 1 by a flip-chip process, such that the foregoing metal bumps 8a and 8b establish a contact with the corresponding wiring patterns 1a and 1b.
In the construction of FIG. 1, it will also be noted that the lower major surface of the substrate 2, which corresponds to the top surface in the mounted state of FIG. 1, is formed with a microlens 2a in correspondence to the diffusion region 5b for focusing an incident optical beam upon the diffusion region 5b. Further, the foregoing lower major surface of the substrate 2 is covered by an anti-reflection film 9 such that the anti-reflection film 9 covers the microlens 2a.
In such a construction of FIG. 1, it will be noted that the p-type diffusion regions 5a and 5b form diodes D1 and D2 respectively, wherein the diode D2 corresponding to the diffusion region 5a acts as a photodiode and detects the incident optical beam. On the other hand, the diode D1 of the diffusion region 5b is connected to the diode D2 in series and drives the same by supplying a drive current. In other words, the diode D1 acts as a drive diode.
FIG. 2 shows an equivalent circuit diagram of the photodetection device 10 of FIG. 1.
Referring to FIG. 2, the photodetection device 10 is connected to a d.c. power supply E that causes a forward biasing of the diode D1 by supplying a drive current I, wherein the drive current I is further supplied, from the diode D1, to the diode D2. Thereby, the diode D2 experiences a reverse biasing and causes a conduction in response to an incident optical beam. Upon conduction of the diode D2, an output signal is obtained at an output terminal.
In such a construction, it should be noted that the diode D1, which merely acts as a drive circuit for supplying the drive current to the diode D2, is allowed to have a large parasitic capacitance, while the diode D2, which is used a photodiode, is required to have a very small parasitic capacitance for high speed response. Thus, the diffusion region 5b has an area much larger than the area of the diffusion region 5a. For example, Makiuchi et al., op. cit teaches that the area of the diffusion region 5b is set 160 times as large as the area of the diffusion region 5a. Thereby, Makiuchi et al. has successfully reduced the parasitic capacitance of the diffusion region 5a to 0.15 pF by forming the circular-shaped diffusion region 5a to have a diameter of about 40 .mu.m. In this case, the diffusion region 5a is formed to have a rectangular shape with a size of 300.times.200 .mu.m. In this case, one obtains a junction capacitance of about 6 pF for the diffusion region 5b.
FIG. 3 shows a semiconductor photodetection integrated circuit in which a number of photodetection devices each having a construction of FIG. 1 are arranged on a common substrate to form an array.
Referring to FIG. 3, the n-type InP substrate 2 carries thereon the n.sup.+ -type InP layer 3 and the undoped InGaAs layer 4, and the layer 4 is covered by the n.sup.- -type InP layer 5 similarly to the construction of FIG. 1. In the example of FIG. 3, the layer 5 includes a number of p.sup.+ -type diffusion regions corresponding to the p-type regions 5a and 5b, wherein there is formed an array of metal bumps including a first row of metal bumps formed of the metal bumps 8a and a second row of metal bumps formed of the metal bumps 8b. It should be noted that each of the metal bumps 8a covers a substantial area of the small diffusion region 5a, while the metal bump 8b covers only a part of the large diffusion region 5b. Thereby, a metal bump 8a generally has an area comparable with that of a metal bump 8b.
The semiconductor photodetection integrated circuit of FIG. 3 is mounted upon a support substrate similar to the substrate 1 of FIG. 1, wherein the integrated circuit is supported by the metal bumps 8a and 8b. It should be noted thereby that, when the metal bumps 8a and 8b are formed to have a similar size, the load or weight of the integrated circuit is distributed uniformly between the metal bumps 8a and the metal bumps 8b. In other words, the diffusion region 5a of the diode D2, of which area is much smaller than the area of the diffusion region 5b, inevitably experiences a vary large mechanical stress. When a mechanical stress is applied to the diffusion region of a photodiode, the photodetection characteristics of the diode are inevitably deteriorated. This problem emerges in the form of increased dark current, for example.
Further, the conventional photodetection integrated circuit of FIG. 3 has another drawback in that the mechanical load applied externally to the metal bump 8a is directly transmitted to the diffusion region 5a of the photodiode D2. It should be noted that the photodetection integrated circuit of FIG. 3 tends to experience an external stress when connecting an optical fiber to the rear side of the layered semiconductor body, wherein the rear side of course corresponds to the top side of the layered semiconductor body when the device is flip-chip mounted upon the support substrate. As the optical fiber is directly connected to the part where the photodiode D2 is formed, the photodetection integrated circuit of such a construction is particularly vulnerable to external stress or shock applied to the optical fiber.
In addition, the photodetection integrated circuit of FIG. 1 or FIG. 3, in which the metal bumps 8a or 8b are generally formed by patterning the conductor layer by a lift-off process, has another drawback in that such a lift-off process wastes valuable materials of the electrode.